The present invention is related to testing of logic circuit designs, in particular in the context of compression of test patterns for logic testing.
Testing of complicated digital logic circuits requires the generation of large test patterns. Unfortunately, the sizes of scan test patterns for today's large designs can be even larger than the sizes of typical tester memory. This necessitates multiple loading of test patterns during a test application and, in turn, increases test application time and test cost. The oversized test pattern set problem is even more severe in delay testing, which has become a necessary test procedure for deep-sub micron chips. Delay test set sizes are often significantly larger than memory capacities of inexpensive testers. Test set sizes and test application times are major factors that determine the test cost of an integrated circuit.
One technique for addressing the issue is to compress the test data. It has been proposed, for example, to use reseeding of a pseudo-random pattern generator (such as a linear feedback shift register), to encode test cubes of difficult to test faults. See B. Könemann, “LFSR-coded Test Patterns for Scan Designs,” Proc. Of European Test Conf., pp. 237-42 (1991). LFSR reseeding has been used for some time to improve fault coverage for random patterns resistant circuits in built-in self-test (BIST). A number of companies have begun to offer test data compaction tools that take advantage of encoding and reseeding techniques to reduce the size of large test patterns—such as Mentor Graphics Embedded Deterministic Test (EDT), Syntest VirtualScan, and Synopsys DBIST/XDBIST. See, e.g., J. Rajski et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,” in Proc. International Test Conference, pp. 301-310 (2002). In general, however, such prior art test compression schemes generate one test pattern from one seed. For example when using either Mentor Graphics EDT or Syntest VirtualScan, one compressed pattern corresponds to one test cube. Syntest VirtuaScan compresses test set sizes by broadcasting; one single test pattern can be shared among multiple scan chains. In order to achieve significant compression rates, typical lengths of scan chains should be split into a larger number of short scan chains. This can result in high routing overhead. Synopsys DBIST/XDBIST does generate a fixed number of test patterns from each seed; however, the additional generated test patterns are not guaranteed to detect any new faults, thereby resulting in disadvantageous increases in test application time.
Accordingly, there is a need for improved test pattern compression which can achieve greater compression rates without unduly increasing test application times.